Electronic device with variable resistance layers and insulating layers alternately stacked and method of manufacturing the same

ABSTRACT

A method of manufacturing an electronic device includes alternately forming first variable resistance layers and insulating layers, forming conductive pillars passing through the first variable resistance layers and the insulating layers, forming a slit passing through the first variable resistance layers and the insulating layers and extending in a first direction, forming openings by etching the first variable resistance layers exposed through the slit, and forming conductive layers in the respective openings.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a continuation of U.S. application Ser. No.16/903,908 filed on Jun. 17, 2020 and claiming priority under 35 U.S.C.§ 119(a) to Korean patent application number 10-2019-0175654, filed onDec. 26, 2019, in the Korean Intellectual Property Office, the entiredisclosure of which is incorporated herein by reference.

BACKGROUND 1. Technical Field

Various embodiments of the present disclosure generally relate to anelectronic device, and more particularly, to an electronic deviceincluding a semiconductor memory and a method of manufacturing theelectronic device.

2. Related Art

Recently, with requirement of miniaturization, low power consumption,high performance, and diversification of electronic apparatuses,semiconductor devices configured to store information are needed invarious electronic apparatuses such as computers and portablecommunication apparatuses. Therefore, there has been research onsemiconductor devices configured to store data using characteristics ofswitching between different resistance phases depending on appliedvoltage or current. Examples of such semiconductor devices include aresistive random access memory (RRAM), a phase-change random accessmemory (PRAM), a ferroelectric random access memory (FRAM), a magneticrandom access memory (MRAM), an E-fuse, and so forth.

SUMMARY

Various embodiments of the present disclosure are directed to anelectronic device having improved operating characteristics andreliability of memory cells, and a method of manufacturing theelectronic device.

An embodiment of the present disclosure may provide for an electronicdevice including a semiconductor memory. The semiconductor memory mayinclude: variable resistance layers and insulating layers alternatelystacked; conductive pillars passing through the variable resistancelayers and the insulating layers; a slit insulating layer passingthrough the insulating layers and extending in a first direction; andconductive layers interposed between the slit insulating layer and thevariable resistance layers. The variable resistance layers may remain inan amorphous state during a program operation.

An embodiment of the present disclosure may provide for an electronicdevice including a semiconductor memory. The semiconductor memory mayinclude: insulating layers stacked; first variable resistance layersalternately stacked with the insulating layers and each extending in afirst direction; vertical bit lines passing through the first variableresistance layers and the insulating layers; a first slit insulatinglayer passing through the insulating layers and extending in the firstdirection; a second slit insulating layer passing through the insulatinglayers and extending in the first direction; first word lines eachinterposed between the first slit insulating layer and each of the firstvariable resistance layers; and second word lines each interposedbetween the second slit insulating layer and each of the first variableresistance layers. First memory cells may be respectively disposedbetween the vertical bit lines and the first word lines, second memorycells may be respectively disposed between the vertical bit lines andthe second word lines, and each of the first memory cells and each ofthe second memory cells are disposed adjacent in a second direction andshare a corresponding one of the first variable resistance layers.

An embodiment of the present disclosure may provide for a method ofmanufacturing an electronic device including a semiconductor memory. Themethod may include: alternately forming first variable resistance layersand insulating layers; forming conductive pillars passing through thefirst variable resistance layers and the insulating layers; forming aslit passing through the first variable resistance layers and theinsulating layers and extending in a first direction; forming openingsby etching the first variable resistance layers exposed through theslit; and forming conductive layers in the respective openings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are diagrams for describing the structure of anelectronic device in accordance with an embodiment of the presentdisclosure.

FIGS. 2A and 2B are diagrams illustrating the structure of asemiconductor device in accordance with an embodiment of the presentdisclosure.

FIGS. 3A and 3B are diagrams illustrating the structure of asemiconductor device in accordance with an embodiment of the presentdisclosure.

FIGS. 4A and 4B are diagrams illustrating the structure of asemiconductor device in accordance with an embodiment of the presentdisclosure.

FIGS. 5A, 5B, and 5C are diagrams illustrating a method of manufacturingan electronic device in accordance with an embodiment of the presentdisclosure.

FIGS. 6A, 6B, and 6C are diagrams illustrating a method of manufacturingan electronic device in accordance with an embodiment of the presentdisclosure.

FIGS. 7A, 7B, 7C, and 7D are diagrams illustrating a method ofmanufacturing an electronic device in accordance with an embodiment ofthe present disclosure.

FIG. 8 is a diagram illustrating the configuration of a microprocessorwhich embodies a memory device in accordance with an embodiment.

FIG. 9 is a diagram illustrating the configuration of a processor whichembodies a memory device in accordance with an embodiment.

FIG. 10 is a diagram illustrating the configuration of a system whichembodies a memory device in accordance with an embodiment.

FIG. 11 is a diagram illustrating the configuration of a data storagesystem which embodies a memory device in accordance with an embodiment.

FIG. 12 is a diagram illustrating the configuration of a memory systemwhich embodies a memory device in accordance with an embodiment.

DETAILED DESCRIPTION

Specific structural or functional descriptions in the embodiments of thepresent disclosure introduced in this specification or application areonly for description of the embodiments of the present disclosure. Thedescriptions should not be construed as being limited to the embodimentsdescribed in the specification or application.

FIGS. 1A and 1B each illustrate a memory cell array of an electronicdevice in accordance with an embodiment of the present disclosure.

Referring to FIG. 1A, the electronic device in accordance with anembodiment of the present disclosure may include a semiconductor memory.The semiconductor memory may include word lines WL, and bit lines BLintersecting with the word lines WL. For reference, the notions of theterms “word lines WL” and “bit lines BL” may be relative to each other.Hence, the word lines WL may be bit lines, and the bit lines BL may beword lines.

The semiconductor memory may include memory cells MC coupled between theword lines WL and the bit lines BL. A plurality of memory cells MC mayshare one bit line BL. The memory cells MC that share the bit line BLmay be respectively coupled to different word lines WL.

Each of the memory cells MC may include a memory element, a selectelement, or a memory element and a select element. Each of the memorycells MC may include a variable resistance layer. The variableresistance layer may have characteristics of making a reversibletransition between different resistance states depending on voltage orcurrent applied thereto. The variable resistance layer may be includedin the memory element or the select element. Alternatively, the variableresistance layer may function as not only a memory element but also aselect element.

The variable resistance layer may include resistance material. Thevariable resistance layer may include transition metal oxide, or metaloxide such as perovskite-based material. Hence, data may be stored inthe memory cell MC by generating or removing an electrical path in thevariable resistance layer.

The variable resistance layer may have an MTJ structure. The variableresistance layer may include a magnetization pinned layer, amagnetization free layer, and a tunnel barrier layer interposedtherebetween. For example, the magnetization pinned layer and themagnetization free layer may include magnetic material. The tunnelbarrier layer may include oxide such as magnesium (Mg), aluminum (Al),zinc (Zn), and titanium (Ti). Here, the magnetization direction of themagnetization free layer may change depending on spin torque ofelectrons in current applied thereto. Therefore, depending on a changein magnetization direction of the magnetization free layer with respectto the magnetization direction of the magnetization pinned layer, datamay be stored in the memory cell MC.

The variable resistance layer may include phase-change material, and mayinclude chalcogenide-based material. The variable resistance layer mayinclude chalcogenide glass, a chalcogenide-based alloy, etc. Thevariable resistance layer may include silicon (Si), germanium (Ge),antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn),selenium (Se), or a combination thereof. For example, the variableresistance layer may have a Ge—Sb—Te (GST) structure, and be formed ofGe₂Sb₂Te₅, Ge₂Sb₂Te₇, Ge₁Sb₂Te₄, or Ge₁Sb₄Te₇. The variable resistancelayer may change in phase depending on a program operation. The variableresistance layer may have a low-resistance crystalline state by a setoperation. The variable resistance layer may have a high-resistanceamorphous state by a reset operation. Therefore, data may be stored inthe memory cell MC by using a difference in resistance depending on thephase of the variable resistance layer.

The variable resistance layer may include variable resistance materialwhich changes in resistance without a phase change, and may includechalcogenide-based material. The variable resistance layer may includegermanium (Ge), antimony (Sb), tellurium (Te), arsenic (As), selenium(Se), silicon (Si), indium (In), tin (Sn), sulfur (S), gallium (Ga), ora combination thereof. The variable resistance layer may have one phaseand retain the phase thereof during a program operation. For example,the variable resistance layer may have an amorphous state, and the phasethereof may not be changed into a crystalline state. Therefore, thethreshold voltage of the memory cell MC may change depending on aprogram pulse applied to the memory cell MC, so that the memory cell MCmay be programmed to at least two types of states. The variableresistance layer may have a high-resistance amorphous state by a resetoperation, so that the memory cell MC may be programmed to a reset statehaving a high threshold voltage. The variable resistance layer may havea low-resistance amorphous state by a set operation, so that the memorycell MC may be programmed to a set state having a low threshold voltage.

Referring to FIG. 1B, the semiconductor memory may include odd wordlines O_WL, even word lines E_WL, vertical bit lines V_BL, and memorycells MC. The odd word lines O_WL and the even word lines E_WL each mayextend in a first direction I.

The vertical bit lines V_BL may each extend in a third direction III.The memory cells MC that are coupled between the vertical bit lines V_BLand the odd word lines O_WL may be referred to as odd memory cells. Thememory cells MC that are coupled between the vertical bit lines V_BL andthe even word lines E_WL may be referred to as even memory cells. Aneven memory cell and an odd memory cell that are disposed in the samelevel with respect to the third direction III and are adjacent to eachother in a second direction II may share an identical vertical bit lineV_BL. Even memory cells that are disposed in the same level with respectto the third direction III and are adjacent to each other in the firstdirection I may share an identical even word line E_WL. Odd memory cellsthat are disposed in the same level with respect to the third directionIII and are adjacent to each other in the first direction I may share anidentical odd word line O_WL. Here, the second direction II may be adirection intersecting with the first direction I. Here, the thirddirection III may be a direction intersecting with the first direction Iand the second direction II. For example, the third direction III may bea direction perpendicular to a plane defined by the first direction Iand the second direction II.

The semiconductor memory may further include switches SW for selectingthe vertical bit lines V_BL. Connection between the vertical bit linesV_BL and the bit lines BL may be controlled by the switches SW. Theswitches SW may include a transistor, a vertical transistor, a diode,etc. In addition, the semiconductor memory may include word lines WL forselectively driving the switches SW.

The word lines WL and the bit lines BL may be used to select a switchSW. One word line WL may be selected from the plurality of word linesWL, and one bit line BL may be selected from the plurality of bit linesBL. Thereby, one switch SW may be selected from the plurality ofswitches SW.

The switches SW may be used to select a vertical bit line V_BL. When theselected switch SW is turned on, the corresponding bit line BL may becoupled with the corresponding vertical bit line V_BL. Hence, onevertical bit line V_BL may be selected from the plurality of verticalbit lines V_BL. Furthermore, one odd word line O_WL may be selected fromthe plurality of odd word lines O_WL or one even word line E_WL may beselected from the plurality of even word lines E_WL. Thereby, a memorycell MC coupled between the selected vertical bit line V_BL and theselected word line O_WL or E_WL may be selected.

FIGS. 2A and 2B are diagrams illustrating the structure of asemiconductor device in accordance with an embodiment of the presentdisclosure. FIG. 2A illustrates a plan view, and FIG. 2B illustrates across section taken along a line A-A′ in the second direction II of FIG.2A. Hereinbelow, repetitive explanation will be omitted for the interestof brevity.

Referring to FIGS. 2A and 2B, the semiconductor device may includevariable resistance layers 21, insulating layers 22, conductive pillars23, conductive layers 24, and a slit insulating layer 25.

The variable resistance layers 21 and the insulating layers 22 arealternately stacked. The variable resistance layers 21 and theinsulating layers 22 may enclose sidewalls of the conductive pillars 23and be stacked in the third direction III. The variable resistancelayers 21 may have characteristics of making a reversible transitionbetween different resistance states depending on voltage or currentapplied thereto. The variable resistance layers 21 may includeresistance material, phase-change material, variable resistancematerial, an MTJ structure, chalcogenide material, etc. The insulatinglayers 22 may be provided to separate the stacked variable resistancelayers 21 from each other. The insulating layers 22 may includeinsulating material such as oxide or nitride.

Each variable resistance layer 21 and each insulating layer 22 may havedifferent widths in the second direction II. Each of the variableresistance layers 21 may have a first width W1. Each of the insulatinglayers 22 may have a second width W2. For example, each of theinsulating layers 22 may have the second width W2 greater than that W1of the variable resistance layers 21. The insulating layers 22 mayprotrude in the second direction II compared to the variable resistancelayers 21. For example, a second portion (e.g., a right portion) of theinsulating layer 22 may protrude farther from the conductive pillar 23than a second portion (e.g., a right portion) of the variable resistancelayer 21 in the second direction II, the second portion of theinsulating layer 22 and the second portion of the variable resistancelayer 21 being disposed adjacent to each other in the third directionIII. A first portion (e.g., a left portion) of the insulating layer 22may protrude farther from the conductive pillar 23 than a first portion(e.g., a left portion) of the variable resistance layer 21 in adirection opposite to the second direction II, the first portion of theinsulating layer 22 and the first portion of the second variableresistance layer 21 being disposed adjacent to each other in the thirddirection III. Portions of each insulating layer 22 that protrudecompared to the variable resistance layer 21, in other words, portionsof the insulating layer 22 that do not overlap with the variableresistance layer 21 with respect to the third direction III, may bedefined as protrusions. For example, a portion of the insulating layer22 may protrude compared to a variable resistance layer 21 such that theportion of the insulating layer 22 protrudes from the variableresistance layer 21 in a cross-sectional view, and the portion of theinsulating layer 22 may be referred to as a protrusion. Each of theinsulating layers 22 may include a first protrusion P1 and a secondprotrusion P2. The first protrusion P1 may protrude compared to a firstsidewall of the variable resistance layer 21. The second protrusion P2may protrude compared to a second sidewall of the variable resistancelayer 21. For example, the first protrusion P1 may protrude from thefirst sidewall of the variable resistance layer 21 and the secondprotrusion P2 may protrude from the second sidewall of the variableresistance layer 21, in a cross-sectional view.

The slit insulating layer 25 may pass through the insulating layers 22and extend in the first direction I. The slit insulating layers 25 mayinclude insulating material such as oxide or nitride.

The conductive pillars 23 each may extend in the third direction III andpass through the variable resistance layers 21 and the insulating layers22. The conductive pillars 23 may be arranged in the first direction Iand the second direction II. The conductive pillars 23 that are arrangedin the first direction I may form one pillar column. Each variableresistance layer 21 may enclose the sidewalls of the conductive pillars23 belonging to a corresponding identical pillar column and extend inthe first direction I. For example, each of the variable resistancelayer 21 may extend in the first direction I and have a plurality ofinner surfaces that respectively enclose a plurality of portions of thesidewalls of the conductive pillars 23 arranged in the first directionI. Therefore, the variable resistance layer 21 may be interposed betweenthe conductive pillars 23 that are adjacent to each other in the firstdirection I. In other words, a plurality of portions of the variableresistance layer 21 each may be interposed between a pair of theconductive pillars 23 that are adjacent to each other in the firstdirection I, thereby filling spaces between the conductive pillars 23.The conductive pillars 23 may be bit lines or vertical bit lines.

The conductive layers 24 may be interposed between the slit insulatinglayer 25 and the variable resistance layers 21. Therefore, the variableresistance layer 21 may be interposed between the conductive layers 24that are adjacent to each other in the second direction II. Theconductive layers 24 may be disposed in the same level as that of thevariable resistance layers 21. For example, with respect to theorientation of FIG. 2B, a top surface of a conductive layer 24 may besubstantially coplanar with a top surface of a corresponding variableresistance layer 21, or a bottom surface of the conductive layer 24 maybe substantially coplanar with a bottom surface of the correspondingvariable resistance layer 21, or both. The conductive layers 24 may bedisposed between the protrusions P1 and P2 that are adjacent to eachother in the third direction III. For example, a conductive layer 24 maybe disposed between a first pair of protrusions P1 and P2 and a secondpair of protrusions P1 and P2, the first pair being disposed adjacent tothe second pair in the third direction III. The conductive layers 24 andthe protrusions P1 and P2 may be alternately stacked.

Each of the conductive layers 24 may be a word line, in detail, an oddword line or an even word line. The conductive layer 24 that is disposedon a first side (e.g., a left side) of the variable resistance layer 21may be a first word line 24A. The conductive layer 24 that is disposedon a second side (e.g., a right side) of the variable resistance layer21 may be a second word line 24B. For example, the second word line 24Bmay be interposed between a first slit insulating layer 25A and thevariable resistance layer 21. In addition, the first word line 24A maybe interposed between a second slit insulating layer 25B disposedadjacent to the first slit insulating layer 25A in the second directionII and the variable resistance layer 21. The first word line 24A may bean even word line, and the second word line 24B may be an odd word line.Alternatively, the first word line 24A may be an odd word line, and thesecond word line 24B may be an even word line.

For reference, although not illustrated, electrode layers may berespectively interposed between the conductive pillars 23 and thevariable resistance layers 21 or between the variable resistance layers21 and the conductive layers 24. In addition, although not illustrated,electrode layers may be respectively interposed between the conductivepillars 23 and the variable resistance layers 21 and between thevariable resistance layers 21 and the conductive layers 24.

According to the above-mentioned structure, memory cells MC1 and MC2 maybe disposed in areas in which the conductive pillars 23 and theconductive layers 24 intersect with each other. Each of the memory cellsMC1 and MC2 may include the conductive layer 24, the variable resistancelayer 21, and the conductive pillar 23.

The first memory cells MC1 may be disposed in areas in which theconductive pillars 23 and the first word lines 24A intersect with eachother. The second memory cells MC2 may be disposed in areas in which theconductive pillars 23 and the second word lines 24B intersect with eachother. The first memory cells MC1 may be arranged in the first directionI. The first memory cells MC1 that are disposed in the same level mayshare the variable resistance layer 21 and the first word line 24A. Thesecond memory cells MC2 may be arranged in the first direction I. Thesecond memory cells MC2 that are disposed in the same level may sharethe variable resistance layer 21 and the second word line 24B.Furthermore, the first memory cell MC1 and the second memory cell MC2that are adjacent to each other in the second direction II may share thevariable resistance layer 21 and the conductive pillars 23 whereas thefirst and second memory cells MC1 and MC2 may be respectively coupled todifferent word lines 24A and 24B.

In an embodiment, the variable resistance layers 21 may includeamorphous chalcogenide. The amorphous chalcogenide may have resistancecorresponding to that of insulating material under a threshold electricfield value. Hence, even if the memory cells MC1 and MC2 share thevariable resistance layer 21, a program operation may be selectivelyperformed. In a selected memory cell, an electric field having anelectric field value greater than the threshold electric field value maybe formed in the variable resistance layer 21, and a memory operationmay be operated in the corresponding area. On the other hand, in thecase of unselected memory cells, an electric field having an electricfield value equal to or less than the threshold electric field value isformed in the variable resistance layer 21. Therefore, the variableresistance layer 21 may have insulating characteristics. Consequently,leakage current may be prevented from occurring in the unselected memorycells.

FIGS. 3A and 3B are diagrams illustrating the structure of asemiconductor device in accordance with an embodiment of the presentdisclosure. FIG. 3A illustrates a plan view, and FIG. 3B illustrates across section taken along a line A-A′ in the second direction II of FIG.3A. Hereinbelow, repetitive explanation will be omitted for the interestof brevity.

Referring to FIGS. 3A and 3B, the semiconductor device may include firstvariable resistance layers 31, second variable resistance layers (e.g.,phase-change layers) 36, insulating layers 32, conductive pillars 33,conductive layers 34, and a slit insulating layer 35.

The first variable resistance layers 31 and the insulating layers 32 arealternately stacked. Each of the insulating layers 32 may have a widthgreater than that of each of the first variable resistance layers 31.For example, each of the insulating layers 32 may have a width in asecond direction II greater than that of each of the first variableresistance layers 31. The insulating layers 32 may protrude in thesecond direction II compared to the first variable resistance layers 31.For example, a second portion (e.g., a right portion) of the insulatinglayer 32 may protrude farther from the conductive pillar 33 than asecond portion (e.g., a right portion) of the first variable resistancelayer 31 in the second direction II, the second portion of theinsulating layer 32 and the second portion of the first variableresistance layer 31 being disposed adjacent to each other in the thirddirection III. A first portion (e.g., a left portion) of the insulatinglayer 32 may protrude farther from the conductive pillar 33 than a firstportion (e.g., a left portion) of the first variable resistance layer 31in a direction opposite to the second direction II, the first portion ofthe insulating layer 32 and the first portion of the first variableresistance layer 31 being disposed adjacent to each other in the thirddirection III. Each of the insulating layers 32 may include a firstprotrusion P1 and a second protrusion P2. The first protrusion P1 mayprotrude compared to a first sidewall of the first variable resistancelayer 31. The second protrusion P2 may protrude compared to a secondsidewall of the first variable resistance layer 31. For example, thefirst protrusion P1 may protrude from the first sidewall of the firstvariable resistance layer 31 and the second protrusion P2 may protrudefrom the second sidewall of the first variable resistance layer 31, in across-sectional view.

The conductive pillars 33 each may extend in the third direction III andpass through the first variable resistance layers 31 and the insulatinglayers 32. Each first variable resistance layer 31 may enclose thesidewalls of the conductive pillars 33 belonging to a correspondingidentical pillar column and extend in the first direction I. Forexample, each of the first variable resistance layer 31 may extend inthe first direction I and have a plurality of inner surfaces thatrespectively enclose a plurality of portions of the sidewalls of theconductive pillars 33 arranged in the first direction I. Therefore, thefirst variable resistance layer 31 may be interposed between theconductive pillars 33 that are adjacent to each other in the firstdirection I. The conductive pillars 33 may be bit lines or vertical bitlines.

The slit insulating layer 35 may pass through the insulating layers 32and extend in the first direction I. The conductive layers 34 may beinterposed between the slit insulating layer 35 and the first variableresistance layers 31. The second variable resistance layers 36 may beinterposed between the first variable resistance layers 31 and theconductive layers 34.

The first variable resistance layers 31, the second variable resistancelayers 36, and the conductive layers 34 may be disposed in substantiallythe same level. The second variable resistance layers 36 and theconductive layers 34 may be disposed between the protrusions P1 and P2that are adjacent to each other in the third direction III. The secondvariable resistance layers 36 and the conductive layers 34 may bealternately stacked with the protrusions P1 and P2 in the thirddirection III.

Each of the conductive layers 34 may be a word line, in detail, an oddword line or an even word line. The first word lines 34A may bealternately stacked with the first protrusions P1. The second word lines34B may be alternately stacked with the second protrusions P2.

The first variable resistance layers 31 and the second variableresistance layers 36 may have characteristics of making a reversibletransition between different resistance states depending on voltage orcurrent applied thereto. The first variable resistance layers 31 and thesecond variable resistance layers 36 may include resistance material,phase-change material, variable resistance material, an MTJ structure,chalcogenide material, etc. In an embodiment, the first variableresistance layers 31 may include chalcogenide and remain in an amorphousstate during a program operation. The second variable resistance layers36 may include phase-change material. In an embodiment, the secondvariable resistance layers 36 may include chalcogenide and bephase-changed into an amorphous state or a crystalline state during theprogram operation.

For reference, although not illustrated, electrode layers may berespectively interposed between the conductive pillars 33 and the firstvariable resistance layers 31, or between the first variable resistancelayers 31 and the second variable resistance layers 36, or between thesecond variable resistance layers 36 and the conductive layers 34.Alternatively, electrode layers may be provided on at least some ofinterfaces of the conductive pillars 33, the first variable resistancelayer 31, the second variable resistance layer 36, and the conductivelayer 34. For example, electrode layers may be provided on two or moreof a first interface between a conductive pillar 33 and a first variableresistance layer 31, a second interface between the first variableresistance layer 31 and a second variable resistance layer 36, and athird interface between the second variable resistance layer 36 and theconductive layer 34.

According to the above-mentioned structure, memory cells MC1 and MC2 maybe disposed in areas in which the conductive pillars 33 and theconductive layers 34 intersect with each other. Each of the memory cellsMC1 and MC2 may include the conductive layer 34, the first variableresistance layer 31, the second variable resistance layer 36, and theconductive pillar 33. The first memory cell MC1 and the second memorycell MC2 that are adjacent to each other in the second direction II mayshare the first variable resistance layer 31, and each may include thesecond variable resistance layer 36. The first variable resistance layer31 may be interposed between a second variable resistance layer 36A ofthe first memory cell MC1 and a second variable resistance layer 36B ofthe second memory cell MC2, so that the second variable resistance layer36A and the second variable resistance layer 36B may be separated fromeach other. Here, the first variable resistance layer 31 may function asa select element. The second variable resistance layer 36 may functionas a memory element.

FIGS. 4A and 4B are diagrams illustrating the structure of asemiconductor device in accordance with an embodiment of the presentdisclosure. FIG. 4A illustrates a plan view, and FIG. 4B illustrates across section taken along a line A-A′ in the second direction II of FIG.4A. Hereinbelow, repetitive explanation will be omitted for the interestof brevity.

Referring to FIGS. 4A and 4B, the semiconductor device may include firstvariable resistance layers 41, second variable resistance layers 46,insulating layers 42, conductive pillars 43, electrode layers 47,conductive layers 44, and a slit insulating layer 45.

The first variable resistance layers 41 and the insulating layers 42 arealternately stacked. The conductive pillars 43 may extend in the thirddirection III and pass through the first variable resistance layers 41and the insulating layers 42. The slit insulating layer 45 may passthrough the insulating layers 42 and extend in the first direction I.

The conductive layers 44 may be interposed between the slit insulatinglayer 45 and the first variable resistance layers 41. Each of theconductive layers 44 may be a word line, in detail, an odd word line oran even word line. The second variable resistance layers 46 may beinterposed between the first variable resistance layers 41 and theconductive layers 44. The second variable resistance layers 46 mayextend between the conductive layers 44 and the insulating layers 42,and each may have a C-shaped cross-section. For example, a secondvariable resistance layer 46 may have a first portion extending in thesecond direction II, a second portion extending in the section directionII and spaced apart from the first portion by a given distance in thethird direction III, and a third portion connecting the first portionand the second portion, each of the first portion and the second portionbeing disposed between a conductive layer 44 and an insulating layer 42.The electrode layers 47 may be interposed between the first variableresistance layers 41 and the second variable resistance layers 46. Theelectrode layers 47 may extend between the conductive layers 44 and theinsulating layers 42, and each may have a C-shaped cross-section. Forexample, each C-shaped second variable resistance layer 46 may be formedin the corresponding C-shaped electrode layer 47. Each electrode layer44 may be formed in the corresponding C-shaped second variableresistance layer 46.

Each of the electrode layers 47 may include tungsten (W), tungstennitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride(TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride(TiAIN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride(TaSiN), tantalum aluminum nitride (TaAIN), carbon (C), silicon carbide(SiC), silicon carbon nitride (SiCN), copper (Cu), zinc (Zn), nickel(Ni), cobalt (Co), lead (Pd), platinum (Pt), or a combination thereof.For example, each of the electrode layers 47 may be a carbon electrode.

For reference, although not illustrated, additional electrode layers maybe interposed between the conductive pillars 43 and the first variableresistance layers 41 or between the second variable resistance layers 46and the conductive layers 44. Alternatively, additional electrode layersmay be interposed between the conductive pillars 43 and the firstvariable resistance layers 41 and between the second variable resistancelayers 46 and the conductive layers 44.

According to the above-mentioned structure, memory cells MC may bedisposed in areas in which the conductive pillars 43 and the conductivelayers 44 intersect with each other. Each of the memory cells MC1 andMC2 may include the conductive pillar 43, the first variable resistancelayer 41, the electrode layers 47, the second variable resistance layer46, and the conductive layer 44.

FIGS. 5A, 5B, and 5C are diagrams illustrating a method of manufacturingan electronic device in accordance with an embodiment of the presentdisclosure. Hereinbelow, repetitive explanation will be omitted for theinterest of brevity.

Referring to FIG. 5A, variable resistance layers 51 and insulatinglayers 52 may be alternately stacked. The variable resistance layers 51may include one or more materials having characteristics of making areversible transition between different resistance states depending onvoltage or current applied thereto. The variable resistance layers 51may include resistance material, phase-change material, variableresistance material, an MTJ structure, chalcogenide material, etc. Forexample, each of the variable resistance layers 51 may include anamorphous chalcogenide layer. Each of the insulating layers 52 mayinclude an oxide layer, a nitride layer, etc.

Thereafter, conductive pillars 53 passing through the variableresistance layers 51 and the insulating layers 52 may be formed. Theconductive pillars 53 may be bit lines or vertical bit lines.Thereafter, a slit SL passing through the variable resistance layers 51and the insulating layers 52 may be formed. The slit SL may be disposedbetween adjacent conductive pillars 53 and extend in one direction. Forexample, the slit SL may be disposed between conductive pillars 53 thatare adjacent in a second direction (e.g., the horizontal direction inFIG. 5A) and extend in a third direction (e.g., the vertical directionin FIG. 5A) intersecting the second direction. The slit SL may furtherextend in a first direction that is perpendicular to the plane definedby the second and third directions.

Referring to FIG. 5B, openings OP may be formed by removing portions ofthe variable resistance layers 51 through the slit SL. The openings OPmay be formed by etching the respective portions of the variableresistance layers 51 to a predetermined depth from the slit SL. Theopenings OP may be formed by selectively etching the variable resistancelayers 51. Therefore, each of the insulating layers 52 may have a widthgreater than that of each of the remaining variable resistance layers51′. Each of the insulating layers 52 may include a protrusion P thatprotrudes compared to the variable resistance layers 51′. The openingsOP may be disposed between the protrusions P and extend in onedirection. For example, each of the openings OP may be disposed betweena pair of protrusions P adjacent in the third direction (e.g., thevertical direction in FIG. 5B) and extend in the second direction (e.g.,the horizontal direction in FIG. 5B). Each of the openings OP mayfurther extend in the first direction that is perpendicular to the planedefined by the second and third directions.

Referring to FIG. 5C, conductive layers 54 may be formed in therespective openings OP. For example, conductive material may be formedin the openings and the slit SL. The conductive material may be formedto have a thickness such that the openings OP are substantiallycompletely filled with the conductive material whereas the slit SL isnot completely filled with the conductive material. Subsequently, theconductive material may be removed from the slit SL. Thereby, theconductive layers 54 that are separated from each other may be formed.Each of the conductive layers 54 may be a word line, in detail, an oddword line or an even word line. The conductive layers 54 may includepolysilicon, or metal such as tungsten. Thereafter, a slit insulatinglayer 55 may be formed in the slit SL.

As a result, memory cells MC may be formed in areas in which theconductive pillars 53 and the conductive layers 54 intersect with eachother. Each of the memory cells MC may include the conductive pillar 53,the variable resistance layer 51, and the conductive layer 54.

According to the above-mentioned manufacturing method, the variableresistance layers 51 and the insulating layers 52 may be alternatelyformed. Subsequently, the variable resistance layers 51 are selectivelyetched and the remaining variable resistance layers 51′ may function asa memory element, or a select element, or both in a memory cell MC. In aconventional technique, a plurality of openings may be formed and then amaterial may be deposited over the plurality of openings to formvariable resistance layers therein. Thus, a deposition method with agood step coverage is required for the conventional technique to formthe variable resistance layers in the plurality of openings. Compared tothe conventional technique in which the variable resistance layers areformed in the openings, a deposition process for the variable resistancelayers 51 may be simplified. For example, an evaporation scheme, such asphysical vapor deposition (PVD) scheme, having a relatively poor stepcoverage may be used to form the variable resistance layers 51. Thus,evaporation of multi-component material such as chalcogenide may befacilitated, and formation of a chalcogenide layer may be easilycontrolled. In addition, a memory cell MC, which includes the remainingvariable resistance layer 51′ including amorphous chalcogenide andfunctions as not only a memory element but also a select element, may beimplemented.

FIGS. 6A, 6B, and 6C are diagrams illustrating a method of manufacturingan electronic device in accordance with an embodiment of the presentdisclosure. Hereinbelow, repetitive explanation will be omitted for theinterest of brevity.

Referring to FIG. 6A, first variable resistance layers 61 and insulatinglayers 62 may be alternately formed. Thereafter, conductive pillars 63passing through the first variable resistance layers 61 and theinsulating layers 62 may be formed. Thereafter, a slit SL passingthrough the variable resistance layers 61 and the insulating layers 62may be formed. The slit SL may be disposed between adjacent conductivepillars 63 and extend in one direction. For example, the slit SL may bedisposed between conductive pillars 63 that are adjacent in a seconddirection (e.g., the horizontal direction in FIG. 6A) and extend in athird direction (e.g., the vertical direction in FIG. 6A) intersectingthe second direction. The slit SL may further extend in a firstdirection that is perpendicular to the plane defined by the second andthird directions.

Referring to FIG. 6B, openings OP may be formed by etching the firstvariable resistance layers 61 through the slit SL. The openings OP maybe disposed in substantially the same level as that of the remainingfirst variable resistance layers 61′ and interposed between theinsulating layers 62.

Referring to FIG. 6C, second variable resistance layers 66 may be formedin the respective openings OR The second variable resistance layers 66may be formed to have a thickness such that the openings OP are notcompletely filled with the second variable resistance layers 66. Forexample, the second variable resistance layers 66 may be selectivelyevaporated on surfaces of the first variable resistance layers 61′through a selective evaporation process.

Thereafter, conductive layers 64 may be formed in the respectiveopenings OP, and then a slit insulating layer 65 may be formed in theslit SL. As a result, memory cells MC may be formed in areas in whichthe conductive pillars 63 and the conductive layers 64 intersect witheach other. Each of the memory cells MC1 and MC2 may include theconductive pillar 63, the first variable resistance layer 61′, thesecond variable resistance layer 66, and the conductive layer 64.

FIGS. 7A, 7B, 7C, and 7D are diagrams illustrating a method ofmanufacturing an electronic device in accordance with an embodiment ofthe present disclosure. Hereinbelow, repetitive explanation will beomitted for the interest of brevity.

Referring to FIG. 7A, first variable resistance layers 71 and insulatinglayers 72 may be alternately formed. Thereafter, conductive pillars 73passing through the first variable resistance layers 71 and theinsulating layers 72 may be formed. Thereafter, a slit SL passingthrough the variable resistance layers 71 and the insulating layers 72may be formed. The slit SL may be disposed between adjacent conductivepillars 73 and extend in one direction. For example, the slit SL may bedisposed between conductive pillars 73 that are adjacent in a seconddirection (e.g., the horizontal direction in FIG. 7A) and extend in athird direction (e.g., the vertical direction in FIG. 7A) intersectingthe second direction. The slit SL may further extend in a firstdirection that is perpendicular to the plane defined by the second andthird directions.

Referring to FIG. 7B, openings OP may be formed by etching the firstvariable resistance layers 71 through the slit SL. The openings OP maybe disposed in substantially the same level as that of the remainingfirst variable resistance layers 71′ and interposed between theinsulating layers 72.

Referring to FIG. 7C, an electrode layer 77, a second variableresistance layer 76, and a conductive layer 74 may be formed. Theelectrode layer 77 and the second variable resistance layer 76 may beformed along inner surfaces of the openings OP and surfaces of theinsulating layers 72. The electrode layer 77 and the second variableresistance layer 76 may be formed to have thicknesses such that theopenings OP are not completely filled with the electrode layer 77 andthe second variable resistance layer 76. For example, a sum of athickness of the electrode layer 77 and a thickness of the secondvariable resistance layer 76 may be smaller than a width of the openingOP in the third direction (e.g., the vertical direction in FIG. 7B). Theconductive layer 74 may be formed on the second variable resistancelayer 76 and fill the openings OP. Thereby, the electrode layer 77, thesecond variable resistance layer 76, and the conductive layer 74 may beformed in the openings OP and the slit SL.

Referring to FIG. 7D, the electrode layer 77, the second variableresistance layer 76, and the conductive layer 74 may be removed from theslit SL. Portions of the electrode layer 77, the second variableresistance layer 76, and the conductive layer 74 may be removed throughthe slit SL. Thereby, each of the openings OP may be filled with theremaining electrode layer 77′, the remaining second variable resistancelayer 76, and the remaining conductive layer 74′.

Thereafter, a slit insulating layer 75 may be formed in the slit SL. Asa result, memory cells MC may be formed in areas in which the conductivepillars 73 and the conductive layers 74 intersect with each other. Eachof the memory cells MC1 and MC2 may include the conductive pillar 73,the first variable resistance layer 71, the electrode layer 77, thesecond variable resistance layer 76, and the conductive layer 74′.

FIG. 8 is a diagram illustrating the configuration of a microprocessor1000 which embodies a memory device in accordance with the embodiment.

Referring to FIG. 8, the microprocessor 1000 may perform tasks forcontrolling and tuning a series of processes of receiving data fromvarious external devices, processing the data, and outputting processingresults to external devices. For example, the microprocessor 1000 mayinclude a memory 1010, an operating component 1020, and a controller1030. The microprocessor 1000 may be various data processors such as acentral processing unit (CPU), a graphic processing unit (GPU), adigital signal processor (DSP) and an application processor (AP).

The memory 1010 may be a circuit configured to store data in themicroprocessor 1000 as a processor register, a register, or the like.For example, the memory 1010 may include a data register, an addressregister, and a floating point register. In addition, the memory 1010may include various registers. The memory 1010 may perform the functionof temporarily storing data for which operations are to be performed bythe operating component 1020, result data of performing the operations,and addresses where data for performing of the operations are stored.

The memory 1010 may include one or more the embodiments of theabove-described electronic devices. For example, the memory 1010 mayinclude: variable resistance layers and insulating layers which arealternately stacked; conductive pillars which pass through the variableresistance layers and the insulating layers; a slit insulating layerwhich passes through the insulating layers and extends in the firstdirection; and conductive layers interposed between the slit insulatinglayer and the variable resistance layers. The variable resistance layersmay retain an amorphous state during a program operation. Thereby, readperformance characteristics of the memory 1010 may be improved.Consequently, the read operation characteristics of the microprocessor1000 may be improved.

The operating component 1020 may perform various four-arithmeticaloperations or logical operations based on results of decoding commandsby the controller 1030. For example, the operating component 1020 mayinclude at least one arithmetic logic unit (ALU).

The controller 1030 may receive signals from, e.g., the memory 1010, theoperating component 1020, and an external device of the microprocessor1000, perform extraction or decoding of commands, and controlling inputand output of signals of the microprocessor 1000, and execute processingrepresented by programs.

The microprocessor 1000 in accordance to the present embodiment mayfurther include a cache memory 1040 which may temporarily store data tobe input from an external device other than the memory 1010 or to beoutput to an external device. In this case, the cache memory 1040 mayexchange data with the memory 1010, the operating component 1020, andthe controller 1030 through a bus interface 1050.

FIG. 9 is a diagram illustrating the configuration of a processor 1100which embodies a memory device in accordance with the embodiment.

Referring to FIG. 9, the processor 1100 may improve performance andrealize multi-functionality by including various functions other thanthose of a microprocessor which performs tasks for controlling andtuning a series of processes of receiving data from various externaldevices, processing the data, and outputting processing results toexternal devices.

The processor 1100 may include a core 1110 which functions as amicroprocessor, a cache memory 1120 configured to temporarily storedata, and a bus interface 1130 configured to transfer data betweeninternal and external devices. The processor 1100 may include varioussystem-on-chips (SoCs) such as a multi-core processor, a graphicprocessing unit (GPU), and an application processor (AP).

The core 1110 in accordance with the present disclosure may be a circuitwhich performs arithmetic logic operations for data input from anexternal device, and may include a memory 1111, an operating component1112, and a controller 1113.

The memory 1111 may be a circuit configured to store data in theprocessor 1100 as a processor register, a register, or the like. Forexample, the memory 1111 may include a data register, an addressregister, and a floating point register. In addition, the memory 1111may include various registers. The memory 1111 may perform the functionof temporarily storing data for which operations are to be performed bythe operating component 1112, result data of performing the operations,and addresses where data for performing of the operations are stored.The operating component 1112 may be a circuit configured to performoperations in the processor 1100, and perform, e.g., variousfour-arithmetical operations or logical operations, based on results ofdecoding commands by the controller 1113. For example, the operatingcomponent 1112 may include at least one arithmetic logic unit (ALU). Thecontroller 1113 may receive signals from, e.g., the memory 1111, theoperating component 1112, and an external device of the processor 1100,perform extraction or decoding of commands, and controlling input andoutput of signals of the processor 1100, and execute processingrepresented by programs.

The cache memory 1120 may be a circuit which temporarily stores data tocompensate for a difference in data processing speed between the core1110 operating at a high speed and an external device operating at a lowspeed. The cache memory 1120 may include a primary storage section 1121,a secondary storage section 1122 and a tertiary storage section 1123.Generally, the cache memory 1120 includes the primary and secondarystorages section 1121 and 1122, and may include the tertiary storagesection 1123 in the case where high storage capacity is required. Asneeded, the number of storage sections included in the cache memory 1120may be increased. In other words, the number of storage sectionsincluded in the cache memory 1120 may be changed depending on design.Here, the speeds at which the primary, secondary and tertiary storagesections 1121, 1122 and 1123 store and discriminate data may be the sameor different from each other. In the case where the speeds of therespective storage sections 1121, 1122 and 1123 are different, the speedof the primary storage section 1121 may be largest. At least one storagesection of the primary storage section 1121, the secondary storagesection 1122 and the tertiary storage section 1123 of the cache memory1120 may include one or more of the electronic devices in accordancewith the above-described embodiments. For example, the cache memory 1120may include: variable resistance layers and insulating layers which arealternately stacked; conductive pillars which pass through the variableresistance layers and the insulating layers; a slit insulating layerwhich passes through the insulating layers and extends in the firstdirection; and conductive layers interposed between the slit insulatinglayer and the variable resistance layers. The variable resistance layersmay retain an amorphous state during a program operation. Thereby, readperformance characteristics of the cache memory 1120 may be improved.Consequently, the read operation characteristics of the processor 1100may be improved.

Although FIG. 9 illustrates that all of the primary, secondary, andtertiary storage sections 1121, 1122 and 1123 are disposed inside thecache memory 1120, all of the primary, secondary and tertiary storagesections 1121, 1122 and 1123 of the cache memory 1120 may be disposedoutside the core 1110 and may compensate for a difference in dataprocessing speed between the core component 1110 and the externaldevice. Alternatively, the primary storage section 1121 of the cachememory 1120 may be disposed inside the core 1110, and the secondarystorage section 1122 and the tertiary storage section 1123 may bedisposed outside the core 1110 to reinforce the function of compensatingfor a difference in data processing speed. As a further alternative, theprimary and secondary storage sections 1121 and 1122 may be disposedinside the core 1110 and the tertiary storage section 1123 may bedisposed outside the core 1110.

The bus interface 1130 may be a circuit which connects the core 1110,the cache memory 1120 and an external device and enhances datatransmission efficiency.

The processor 1100 in accordance with the present embodiment may includea plurality of cores 1110. The plurality of cores 1110 may share thecache memory 1120. The plurality of cores 1110 and the cache memory 1120may be directly connected or be connected through the bus interface1130. The plurality of cores 1110 may be configured in the same way asthe above-described configuration of the core 1110. In the case wherethe processor 1100 includes the plurality of cores 1110, the primarystorage section 1121 of the cache memory 1120 may be configured in eachcore 1110 based on the number of cores 1110, and the secondary storagesection 1122 and the tertiary storage section 1123 may be configuredoutside the plurality of cores 1110 in such a way as to be sharedthrough the bus interface 1130. Here, the processing speed of theprimary storage section 1121 may be higher than that of the secondary ortertiary storage section 1122 or 1123. In an embodiment, the primarystorage section 1121 and the secondary storage section 1122 may beconfigured in each core 1110 based on the number of cores 1110, and thetertiary storage section 1123 may be configured outside the plurality ofcores 1110 in such a way as to be shared through the bus interface 1130.

The processor 1100 in accordance with the present embodiment may furtherinclude, e.g., an embedded memory 1140 configured to store data, acommunication module 1150 configured to transceive data with an externaldevice in a wired or wireless manner, a memory controller 1160configured to drive an external memory device, and a media processor1170 configured to process the data processed in the processor 1100 orthe data input from an external input device and output the processeddata to an external interface device. In addition, the processor 1100may include a plurality of modules and devices. In this case, theplurality of modules that are additionally provided may exchange datawith the cores 1110 and the cache memory 1120 and with one another,through the bus interface 1130.

The embedded memory 1140 may include not only a volatile memory but alsoa nonvolatile memory. Examples of the volatile memory may include, e.g.,a dynamic random access memory (DRAM), a mobile DRAM, a static randomaccess memory (SRAM), and a memory having functions similar to that ofthe foregoing memories. Examples of the nonvolatile memory may include aread only memory (ROM), a NOR flash memory, a NAND flash memory, a phasechange random access memory (PRAM), a resistive random access memory(RRAM), a spin transfer torque random access memory (STTRAM), a magneticrandom access memory (MRAM), and a memory having functions similar tothat of the foregoing memories.

The communication module 1150 may include a module capable of beingconnected with a wired network, a module capable of being connected witha wireless network, or both of them. The wired network module mayinclude, e.g., a local area network (LAN), a universal serial bus (USB),an Ethernet, or power line communication (PLC), which is operated in amanner similar to that of various devices configured to transceive datathrough transfer lines. The wireless network module may include infrareddata association (IrDA), code division multiple access (CDMA), timedivision multiple access (TDMA), frequency division multiple access(FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN),Bluetooth, radio frequency identification (RFID), long term evolution(LTE), near field communication (NFC), a wireless broadband Internet(Wibro), high speed downlink packet access (HSDPA), wideband CDMA(CDMA), or ultra wideband (UWB), in a manner similar to that of variousdevices configured to transceive data without a separate transfer line.

The memory controller 1160 may process and manage data which istransmitted between the processor 1100 and external storage devicesconfigured to operate according to different communication standards.The memory controller 1160 may include various memory controllers, forexample, controllers which may control integrated device electronics(IDE), serial advanced technology attachment (SATA), small computersystem interface (SCSI), redundant array of independent disks (RAID), asolid state disk (SSD), external SATA (eSATA), personal computer memorycard international association (PCMCIA), a universal serial bus (USB), asecure digital (SD) card, a mini secure digital (mSD) card, a microsecure digital (micro SD) card, a secure digital high capacity (SDHC)card, a memory stick card, a smart media (SM) card, a multimedia card(MMC), an embedded MMC (eMMC), and a compact flash (CE) card.

The media processor 1170 may process the data processed in the processor1100 or the data input in the forms of image, sound, and others from theexternal input device, and output the data to the external interfacedevice. The media processor 1170 may include, e.g., a graphic processingunit (GPU), a digital signal processor (DSP), a high definition audiodevice (HD audio), a high definition multimedia interface (HDMI)controller.

FIG. 10 is a diagram illustrating the configuration of a system 1200which embodies a memory device in accordance with the embodiment.

Referring to FIG. 10, the system 1200 may function as a device forprocessing data and perform input, processing, output, communication,storage, etc. to conduct a series of operations of managing data. Thesystem 1200 may include, e.g., a processor 1210, a main memory device1220, an auxiliary memory device 1230, and an interface device 1240.Examples of the system 1200 in accordance with the present embodimentmay include various electronic systems configured to operate usingprocessors such as a computer, a server, a personal digital assistant(PDA), a portable computer, a web tablet, a wireless phone, a mobilephone, a smart phone, a digital music player, a portable multimediaplayer (PMP), a camera, a global positioning system (GPS), a videocamera, a voice recorder, telematics, an audio visual (AV) system, and asmart television.

The processor 1210 may control operations of decoding input commands andprocessing calculation, comparison, etc. for the data stored in thesystem 1200. The processor 1210 may include, e.g., a microprocessor unit(MPU), a central processing unit (CPU), a single/multi-core processor, agraphic processing unit (GPU), an application processor (AP), and adigital signal processor (DSP).

The main memory device 1220 may be a memory which can receive, whenprograms are executed, program codes or data from the auxiliary memorydevice 1230 and store and execute the program codes or data and canconserve memorized contents even when the power supply is interrupted.The main memory device 1220 may include one or more of the electronicdevices in accordance with the above-described embodiments. For example,the main memory device 1220 may include: variable resistance layers andinsulating layers which are alternately stacked; conductive pillarswhich pass through the variable resistance layers and the insulatinglayers; a slit insulating layer which passes through the insulatinglayers and extends in the first direction; and conductive layersinterposed between the slit insulating layer and the variable resistancelayers. The variable resistance layers may retain an amorphous stateduring a program operation. Thereby, read performance characteristics ofthe main memory device 1220 may be improved. Consequently, the readoperation characteristics of the system 1200 may be improved.

The main memory device 1220 may further include a static random accessmemory (SRAM), a dynamic random access memory (DRAM), and so on, of avolatile memory type in which all contents are erased when power supplyis interrupted. Unlike this, the main memory device 1220 may not includethe electronic devices in accordance with the foregoing embodiment, butmay include a static random access memory (SRAM), a dynamic randomaccess memory (DRAM), and so on, of a volatile memory type in which allcontents are erased when the power supply is interrupted.

The auxiliary memory device 1230 may be a memory device configured tostore program codes or data. Although the speed of the auxiliary memorydevice 1230 is slower than the main memory device 1220, the auxiliarymemory device 1230 can store a relatively large amount of data. Theauxiliary memory device 1230 may include one or more of the electronicdevices in accordance with the above-described embodiments. For example,the auxiliary memory device 1230 may include: variable resistance layersand insulating layers which are alternately stacked; conductive pillarswhich pass through the variable resistance layers and the insulatinglayers; a slit insulating layer which passes through the insulatinglayers and extends in the first direction; and conductive layersinterposed between the slit insulating layer and the variable resistancelayers. The variable resistance layers may retain an amorphous stateduring a program operation. Thereby, read performance characteristics ofthe auxiliary memory device 1230 may be improved. Consequently, the readoperation characteristics of the system 1200 may be improved.

Also the auxiliary memory device 1230 may further include, e.g., a datastorage system (refer to reference numeral 1300 of FIG. 11) such as amagnetic tape or a magnetic disk using magnetism, a laser disk usingoptics, a magneto-optical disc using both magnetism and optics, a solidstate disk (SSD), a USB memory (universal serial bus memory), a securedigital (SD) card, a mini secure digital (mSD) card, a micro securedigital (micro SD) card, a secure digital high capacity (SDHC) card, amemory stick card, a smart media (SM) card, a multimedia card (MMC), anembedded MMC (eMMC), and a compact flash (CF) card. Unlike this, theauxiliary memory device 1230 may not include the electronic devices inaccordance with the foregoing embodiment, but may further include, e.g.,data storage systems (refer to reference numeral 1300 of FIG. 11) suchas a magnetic tape or a magnetic disk using magnetism, a laser diskusing optics, a magneto-optical disc using both magnetism and optics, asolid state disk (SSD), a USB memory (universal serial bus memory), asecure digital (SD) card, a mini secure digital (mSD) card, a microsecure digital (micro SD) card, a secure digital high capacity (SDHC)card, a memory stick card, a smart media (SM) card, a multimedia card(MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

The interface device 1240 may perform exchange of commands and databetween the system 1200 of the present embodiment and an externaldevice. For example, the interface device 1240 may be a keypad, akeyboard a mouse, a speaker, a mike, a display, various human interfacedevices (HIDs), or a communication device. The communication device mayinclude a module capable of being connected with a wired network, amodule capable of being connected with a wireless network, or both ofthem. The wired network module may include, e.g., a local area network(LAN), a universal serial bus (USB), an Ethernet, or a power linecommunication (PLC), which is operated in a manner similar to that ofvarious devices configured to transceive data through transfer lines.The wireless network module may include, e.g., infrared data association(IrDA), code division multiple access (CDMA), time division multipleaccess (TDMA), frequency division multiple access (FDMA), a wirelessLAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radiofrequency identification (RFID), long term evolution (LTE), near fieldcommunication (NFC), a wireless broadband Internet (Wibro), high speeddownlink packet access (HSDPA), wideband CDMA (WCDMA), or ultra wideband(UWB), which is operated in a manner similar to that of various devicesconfigured to transceive data without a separate transfer line.

FIG. 11 is a diagram illustrating the configuration of a data storagesystem 1300 which embodies a memory device in accordance with theembodiment.

Referring to FIG. 11, the data storage system 1300 may include a storagedevice 1310 which has a nonvolatile characteristic as a component forstoring data, a controller 1320 configured to control the storage device1310, an interface 1330 for connection with an external device, and atemporary storage device 1340 configured to temporarily store data. Thedata storage system 1300 may be a disk type such as a hard disk drive(HDD), a compact disc read only memory (CDROM), a digital versatile disc(DVD), or a solid state disk (SSD), or a card type such as a USB memory(universal serial bus memory), a secure digital (SD) card, a mini securedigital (mSD) card, a micro secure digital (micro SD) card, a securedigital high capacity (SDHC) card, a memory stick card, a smart media(SM) card, a multimedia card (MMC), an embedded MMC (eMMC), or a compactflash (CF) card.

The storage device 1310 may include a nonvolatile memory which storesdata semi-permanently. Examples of the nonvolatile memory may include aread only memory (ROM), a NOR flash memory, a NAND flash memory, a phasechange random access memory (PRAM), a resistive random access memory(RRAM), and a magnetic random access memory (MRAM).

The controller 1320 may control data exchange between the storage device1310 and the interface 1330. To this end, the controller 1320 mayinclude a processor 1321 for performing, e.g., an operation forprocessing commands input through the interface 1330 from an externaldevice provided outside the data storage system 1300.

The interface 1330 may perform exchange of commands and data between thedata storage system 1300 and an external device. In the case where thedata storage system 1300 is a card type system, the interface 1330 maybe compatible with interfaces which are used in devices, such as a USBmemory (universal serial bus memory), a secure digital (SD) card, a minisecure digital (mSD) card, a micro secure digital (micro SD) card, asecure digital high capacity (SDHC) card, a memory stick card, a smartmedia (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), and acompact flash (CF) card, or be compatible with interfaces which are usedin devices similar to the foregoing devices. In the case where the datastorage system 1300 is a disk type system, the interface 1330 may becompatible with interfaces such as an integrated device electronics(IDE), a serial advanced technology attachment (SATA), a small computersystem interface (SCSI), an external SATA (eSATA), a personal computermemory card international association (PCMCIA), and a universal serialbus (USB), or be compatible with the interfaces similar to the foregoinginterfaces. The interface 1330 may be compatible with one or moreinterfaces having different types.

The temporary storage device 1340 may temporarily store data to improvedata transfer efficiency between the interface 1330 and the storagedevice 1310 according to diversifications and high performance of aninterface with an external device, a controller and a system. Thetemporary memory device 1340 may include one or more of the electronicdevices in accordance with the foregoing embodiments. For example, thetemporary storage device 1340 may include: variable resistance layersand insulating layers which are alternately stacked; conductive pillarswhich pass through the variable resistance layers and the insulatinglayers; a slit insulating layer which passes through the insulatinglayers and extends in the first direction; and conductive layersinterposed between the slit insulating layer and the variable resistancelayers. The variable resistance layers may retain an amorphous stateduring a program operation. Thereby, read performance characteristics ofthe temporary storage device 1340 may be improved. Consequently, theread operation characteristics of the data storage system 1300 may beimproved.

FIG. 12 is a diagram illustrating the configuration of a memory system1400 which embodies a memory device in accordance with the embodiment.

Referring to FIG. 12, the memory system 1400 may include, e.g., a memory1410 having nonvolatile characteristics as a component for storing data,a memory controller 1420 configured to control the memory 1410, aninterface 1430 for connection with an external device. Also theauxiliary memory device 1400 may be a card type system such as a solidstate disk (SSD), a USB memory (universal serial bus memory), a securedigital (SD) card, a mini secure digital (mSD) card, a micro securedigital (micro SD) card, a secure digital high capacity (SDHC) card, amemory stick card, a smart media (SM) card, a multimedia card (MMC), anembedded MMC (eMMC), or a compact flash (CF) card.

The memory 1410 configured to store data may include one or more of theelectronic devices in accordance with the foregoing embodiments. Forexample, the memory 1410 may include: variable resistance layers andinsulating layers which are alternately stacked; conductive pillarswhich pass through the variable resistance layers and the insulatinglayers; a slit insulating layer which passes through the insulatinglayers and extends in the first direction; and conductive layersinterposed between the slit insulating layer and the variable resistancelayers. The variable resistance layers may retain an amorphous stateduring a program operation. Thereby, read performance characteristics ofthe memory 1410 may be improved. Consequently, the read operationcharacteristics of the memory system 1400 may be improved.

Examples of the nonvolatile memory in accordance with the presentembodiment may include a read only memory (ROM), a NOR flash memory, aNAND flash memory, a phase change random access memory (PRAM), aresistive random access memory (RRAM), and a magnetic random accessmemory (MRAM).

The memory controller 1420 may control data exchange between the memory1410 and the interface 1430. To this end, the memory controller 1420 mayinclude a processor 1421 for performing, e.g., an operation forprocessing commands input through the interface 1430 from an externaldevice provided outside the data storage system 1400.

The interface 1430 may perform exchange of commands and data between thememory system 1400 and the external device. The interface 1430 may becompatible with interfaces which are used in devices, such as auniversal serial bus (USB) memory, a secure digital (SD) card, a minisecure digital (mSD) card, a micro secure digital (micro SD) card, asecure digital high capacity (SDHC) card, a memory stick card, a smartmedia (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), acompact flash (CF) card, or be compatible with interfaces which are usedin devices similar to the foregoing devices. The interface 1430 may becompatible with one or more interfaces having different types.

The memory system 1400 in accordance with the present embodiment mayfurther include a buffer memory 1440 for improving data transferefficiency between the interface 1430 and the memory 1410 according todiversification and high performance of an interface with an externaldevice, a memory controller, and a memory system. The buffer memory 1440configured to temporarily store data may include one or more of theelectronic devices in accordance with the foregoing embodiments. Forexample, the buffer memory 1440 may include: variable resistance layersand insulating layers which are alternately stacked; conductive pillarswhich pass through the variable resistance layers and the insulatinglayers; a slit insulating layer which passes through the insulatinglayers and extends in the first direction; and conductive layersinterposed between the slit insulating layer and the variable resistancelayers. The variable resistance layers may retain an amorphous stateduring a program operation. Consequently, the read operationcharacteristics of the memory system 1400 may be improved.

In addition, examples of the buffer memory 1440 in accordance with thepresent embodiment may further include, e.g., a static random accessmemory (SRAM), and a dynamic random access memory (DRAM), which have avolatile characteristic, and a phase change random access memory (PRAM),a resistive random access memory (RRAM), a spin transfer torque randomaccess memory (STTRAM), and a magnetic random access memory (MRAM),which have a nonvolatile characteristic. Unlike this, examples of thebuffer memory 1440 may not include the electronic device in accordancewith the foregoing embodiment, but may further include, e.g., a staticrandom access memory (SRAM), and a dynamic random access memory (DRAM),which have a volatile characteristic, and a phase change random accessmemory (PRAM), a resistive random access memory (RRAM), a spin transfertorque random access memory (STTRAM), and a magnetic random accessmemory (MRAM), which have a nonvolatile characteristic.

Various embodiments of the present disclosure may provide an electronicdevice having improved operating characteristics and reliability ofmemory cells.

Examples of embodiments have been disclosed herein, and althoughspecific terms are employed, they are used and are to be interpreted ina generic and descriptive sense only and not for purpose of limitation.In some instances, as would be apparent to one of ordinary skill in theart as of the filing of the present application, features,characteristics, and/or elements described in connection with aparticular embodiment may be used singly or in combination withfeatures, characteristics, and/or elements described in connection withother embodiments unless otherwise specifically indicated. Accordingly,it will be understood by those of skill in the art that various changesin form and details may be made without departing from the spirit andscope of the present disclosure as set forth in the following claims.

What is claimed is:
 1. A method of manufacturing an electronic deviceincluding a semiconductor memory, the method comprising: alternatelyforming first variable resistance layers and insulating layers; formingconductive pillars passing through the first variable resistance layersand the insulating layers; forming a slit passing through the firstvariable resistance layers and the insulating layers and extending in afirst direction; forming openings by etching the first variableresistance layers exposed through the slit; and forming conductivelayers in the respective openings.
 2. The method according to claim 1,further comprising forming a slit insulating layer in the slit afterforming the conductive layers.
 3. The method according to claim 1,wherein the first variable resistance layers include amorphouschalcogenide.
 4. The method according to claim 1, further comprisingforming second variable resistance layers in the openings before formingthe conductive layers.
 5. The method according to claim 4, wherein thefirst variable resistance layers include amorphous chalcogenide, and thesecond variable resistance layers include phase-change material.
 6. Themethod according to claim 1, wherein the first variable resistancelayers are formed using a physical vapor deposition process.
 7. Themethod according to claim 1, further comprising forming electrode layersin the openings and the slit, before the conductive layers are formed.8. The method according to claim 7, further comprising forming secondvariable resistance layers in the openings and the slit where theelectrode layers are formed, wherein a sum of a thickness of each of theelectrode layers and a thickness of each of the second variableresistance layers is smaller than a width of each of the openings in asecond direction intersecting the first direction.
 9. The methodaccording to claim 8, further comprising removing portions of theelectrode layers, the second variable resistance layers, and theconductive layers through the slit.
 10. The method according to claim 9,wherein, after the removal is performed, remaining portions of theelectrode layers and remaining portions of the second variableresistance layers each have a C-shaped cross-section.